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Raspberry Pi /RP2040 /DMA /INTR

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Interpret as INTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INTR

Description

Interrupt Status (raw)

Fields

INTR

Raw interrupt status for DMA Channels 0…15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.

Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.

This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.

It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.

Links

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Register License

Copyright © 2020 Raspberry Pi (Trading) Ltd.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data